As chip capacity continues to significantly increase, the use of programmable gate arrays (PGAs), particularly field programmable gate arrays (FPGAs), is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized chip that is designed for a particular application. Notably, an FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity and flexibility of FPGA's. Importantly, FPGAs can be designed using a variety of architectures, which can include user configurable input/output blocks (IOBs) and programmable/configurable logic blocks (PLBs/CLBs) having configurable interconnects and switching capability. The CLBs, IOBs, and interconnect structure are typically programmed by loading a bitstream of configuration data into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream is typically loaded from an external memory, for example, from and an external programmable read only memory (PROM) or similar device. The collective states of the individual memory cells determine the functions of the FPGA.
As advancements in computer chip technology continue to increase the threshold on the number of CLBs, IOBs and interconnect structure in FPGAs, it has become possible to build entire data processing systems inside the FPGA. These processing systems are typically called embedded processors or controllers. An embedded processor or controller can be microprocessor or microcontroller circuitry that has been integrated into an electronic device, such as an FPGA, as opposed to being built as a standalone module or “plugin card.” Moreover, advancements in FPGA technology has also led to the development of FPGA-based system-on-chip (SoC), including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, a SoC can include all required ancillary electronics. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. FPGA-based SoCs with embedded operating systems (OSs) have further enhanced their popularity and flexibility.
FPGA-based SoCs have resulted in the proliferation of numerous consumer devices such as wireless telephones, personal digital assistants (PDAs), and digital cameras. In order for device manufacturers to develop FPGA-based SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or IP cores. An electronic file containing component information can typically be used to represent the core. A device manufacturer will generally acquire rights for one or more IP cores that are integrated to fabricate the SoC.
One of the most important resources in data processing systems including consumer devices is memory. Many FPGAs provide blocks of random access memories (RAMs), each having thousands of memory cells (called “block RAMs” or BRAMS). BRAMS are known in the art. Notwithstanding, the flexibility of the blocks permit a variety of memory configurations. For example, a BRAM having a capacity of 16 Kilobits can be configured to have an address depth of either 16K, 8K, 4K, 2K, 1K and 0.5K, with the corresponding number of bits per address as 1, 2, 4, 8, 16 or 32, respectively. Additionally, a number of blocks can be combined to increase the total memory size. During operation of the FPGA, the BRAMs can be used to store information such as system configuration data, program data, and operational data. For example, configuration information used during initialization of a data processing device can be stored in the BRAM.
The high level structure of an FPGA comprises the FPGA fabric, which can include a processor block, and BRAMs. The processor block can include an IP core surrounded by supporting logic circuitry, known in the art as “gasket logic.” Residing within the gasket logic are on-chip memory (OCM) controllers configured to control the flow of data between the BRAMS and the IP core. The OCM controllers typically have control registers which store configuration information, which can be used for initialization and performing particular functions.
One major disadvantage with existing data processing systems and devices that utilize FPGAs is that the on-chip devices such as the OCM controllers have to wait for the system or device to be initialized before the control registers are configured. Generally, the on-chip device control or configuration registers are loaded at runtime, which occurs after the data processing system or device has been powered up and has executed its startup routines. The more extensive the startup routines, the longer it will take to load values in the control registers during system initialization. Consequently, boot and startup times for these data processing systems and devices can be unnecessarily extended.
Given these and other inherent drawbacks, there is a need for a method and system for controlling default value of flip-flops used as configuration registers in PGA/ASIC-based designs.